Data communication between two points always requires some method of determining when data is valid on the medium and can therefore be sampled for capture. This implies some form of synchronization between the sender and receiver of the data. The most obvious method is to transmit a synchronization signal along with the data signal to tell the receiver when to capture. This method is used extensively, especially when serial data is being transferred. This method has costs associated with extra cabling for the sync signal and extra power required in the sender. Another method involves embedding synchronization elements within the data stream itself such that the receiver can determine the optimum sampling point. In this scheme data is generally transferred in bursts, or packets, and the receiver also has to detect when a packet has begun.
The second method generally involves the use of a phase locked loop to keep the internal sampling signal in sync with the received data. Both analog and digital phase locked loops (PLL) have been used. The analog PLL modulates the phase of a clock to align it to the data. The digital PLL uses a high frequency clock and then selects which of the multiple edges of the clock that occur during one data bit time that is closest to the center. Many methods can be used with either the analog or digital PLL to notify the receiver when a new data packet has begun. One popular method is to use a distinct non-data start bit to signal the occurrence of a data packet.
Analog phase locked loop solutions are not desirable because they are prone to noise induced sampling errors. Improvements over the analog sampling technique involved the use of digital sampling approaches to avoid the noise problem. However, a problem with using digital sampling is metastability. The output of a digital latch may be indeterminate for a period of time if inputs to the latch switch concurrently. Therefore, during the time when the latch output is indeterminate, an incorrect data value may exist until the output has time to stabilize. Further improvements in digital sampling are needed.
The invention described herein uses an adaptation of the digital PLL scheme in which a string of delay buffers are used to match the data frequency. Each buffer in the string produces an edge which can be used for sampling the data, similar to the multiple edges provided by a higher frequency clock. One potential problem lies in determining the optimum sampling point by using the start bit edge to examine all the phase edges available. Since the start bit edge is inherently asynchronous with respect to the phase edges, the potential for metastability cannot be ignored. This invention uses an additional delay circuit to allow any metastability a chance to resolve itself before the sampled phase edges are propagated.
It is accordingly an object of the invention to provide a digital data sampling circuit which avoids sampling errors due to switching noise. It is a further object of the invention to provide a digital sampling circuit that is less susceptible to metastability problems.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings herein.